1. Field of the Invention
The present invention generally relates to testing integrated circuits, and more particularly to testing clock circuits implemented in integrated circuits.
2. Description of Related Art
During manufacturing of an integrated circuit, various tests are performed to determine whether various circuits in the integrated circuit conform to desired specifications. Some of these circuits are clock circuits that generate an output clock signal based on an input clock signal and a feedback clock signal. The feedback clock signal is derived from the output clock signal and is used to generate the output clock signal at a desired frequency. One type of clock circuit that generates an output clock signal based on an input clock signal and a feedback clock signal is a phase-locked loop circuit. A phase-locked loop circuit locks a frequency and phase of a feedback clock signal to a frequency of an input clock signal. Another type of clock circuit that generates an output clock signal based on an input clock signal and a feedback clock signal is a delay-locked loop circuit. A delay-locked loop circuit locks a frequency of a feedback clock signal to a frequency of an input clock signal. Additionally, the delay-locked loop circuit delays the input clock signal by one or more clock periods to generate the output clock signal.
In many cases, an integrated circuit tester does not operate at the frequency of an output clock signal of the clock circuit. To determine whether the frequency of the feedback clock signal is locked to the frequency of the input clock signal, various techniques employ test circuitry in the integrated circuit. The test circuitry performs a test on the clock circuit to determine whether the frequency of the feedback clock signal is locked to the frequency of the input clock signal of the clock circuit. An integrated circuit tester can then determine whether the frequency of the feedback clock signal is locked to the frequency of the input clock signal based on a result of the test performed by the test circuitry. Moreover, if the frequency of the feedback clock signal is determined to be locked to the frequency of the input clock signal, the frequency of the output clock signal may be determined to be within a specified frequency range.
One technique that uses test circuitry for determining whether the frequency of a feedback clock signal of a clock circuit is locked to an input clock signal of the clock circuit employs two counters. One counter counts the number of clock cycles of the input clock signal during a test interval and the other counter counts the number of clock cycles of the feedback clock signal during the test interval. A tester then determines whether the frequency of the output clock signal is locked to the frequency of the input clock signal based on the values of the counters. Because it is difficult to start the counters at precisely the same time, the frequency of the feedback clock signal is determined to be locked to the frequency of the input clock signal if the frequency of the feedback clock signal is within a tolerance of the frequency of the input clock signal.
Typically, the frequency of the feedback clock signal is determined to be locked to the frequency of the input clock signal if the number of clock cycles of the feedback clock signal and the number of clock signals of the input clock signal in a test interval do not differ by more than one. In this case, the tolerance of the frequency of the input clock signal is the reciprocal of the number of clock cycles of the input clock signal in the test interval. Generally, the tolerance may be decreased by increasing the test interval, which increases the number of clock cycles of the input clock signal in the test interval. Increasing the test interval, however, consumes valuable test time in testing the integrated circuit. Moreover, it may be desirable in some circumstances to determine whether the frequency of the output clock signal is above a threshold frequency of a frequency range regardless of whether the frequency of the feedback clock signal is locked to the frequency of the input clock signal.
In light of the above, a need exists for reducing the time required for determining whether the frequency of a feedback clock signal of a clock circuit is locked to the frequency of an input clock signal of the clock circuit. A further need exists for reducing the time required for determining whether a frequency of an output clock signal of a clock circuit is above a threshold frequency.